// SPDX-License-Identifier: GPL-2.0-or-later or MIT

/include/ "fsl/p1020si-pre.dtsi"

#include <dt-bindings/gpio/gpio.h>		  

/ {
	model = "Extreme Networks WS-AP3825i";
	compatible = "extreme-networks,ws-ap3825i";

	aliases {
		led-boot = &led_power_green;
		led-failsafe = &led_power_red;
		led-running = &led_power_green;
		led-upgrade = &led_power_red;
	};

	memory {
		device_type = "memory";
	};

	led_spi {
		compatible = "spi-gpio";
		#address-cells = <1>;
		#size-cells = <0>;

		sck-gpios = <&gpio0 14 0>;
		mosi-gpios = <&gpio0 13 0>;
		num-chipselects = <0>;

		led_gpio: led_gpio@0 {
			compatible = "fairchild,74hc595";
			reg = <0>;
			gpio-controller;
			#gpio-cells = <2>;
			registers-number = <8>;
			spi-max-frequency = <100000>;
		};
	};

	leds {
		compatible = "gpio-leds";

		wifi1 {
			gpios = <&led_gpio 3 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3825i:green:radio1";
			linux,default-trigger = "phy0tpt";
		};

		wifi2 {
			gpios = <&led_gpio 2 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3825i:green:radio2";
			linux,default-trigger = "phy1tpt";
		};

		led_power_green: power_green {
			gpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3825i:green:power";
		};

		led_power_red: power_red {
			gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3825i:red:power";
		};

		eth0_red {
			gpios = <&led_gpio 6 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3825i:red:eth0";
		};

		eth0_green {
			gpios = <&led_gpio 4 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3825i:green:eth0";
		};

		eth1_red {
			gpios = <&led_gpio 7 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3825i:red:eth1";
		};

		eth1_green {
			gpios = <&led_gpio 5 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3825i:green:eth1";
		};
	};

	keys {
		compatible = "gpio-keys";

		reset {
			label = "Reset button";
			gpios = <&gpio0 1 1>; /* active low */
			linux,code = <0x198>; /* KEY_RESTART */
		};
	};

	lbc: localbus@ffe05000 {
		reg = <0 0xffe05000 0 0x1000>;
		ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;

		nor@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x4000000>;
			bank-width = <2>;
			device-width = <1>;

			partitions {
				compatible = "fixed-partitions";
				#address-cells = <1>;
				#size-cells = <1>;

				partition@0 {
					compatible = "denx,fit";
					reg = <0x0 0x3d60000>;
					label = "firmware";
				};

				partition@3d60000 {
					reg = <0x3d60000 0x20000>;
					label = "calib";
					read-only;
				};

				partition@3d80000{
					reg = <0x3d80000 0x80000>;
					label = "u-boot";
					read-only;
				};

				partition@3e00000{
					reg = <0x3e00000 0x100000>;
					label = "nvram";
					read-only;
				};

				partition@3f00000 {
					reg = <0x3f00000 0x20000>;
					label = "cfg2";
					read-only;
				};

				partition@3f20000 {
					reg = <0x3f20000 0x20000>;
					label = "cfg1";
					read-only;
				};
			};
		};
	};

	soc: soc@ffe00000 {
		ranges = <0x0 0x0 0xffe00000 0x100000>;

		gpio0: gpio-controller@fc00 {
		};

		mdio@24000 {
			phy0: ethernet-phy@0 {
				interrupts = <3 1 0 0>;
				reg = <0x5>;
			};

			phy2: ethernet-phy@2 {
				interrupts = <1 1 0 0>;
				reg = <0x6>;
			};
		};

		mdio@25000 {
			status = "disabled";
		};

		mdio@26000 {
			status = "disabled";
		};

		enet0: ethernet@b0000 {
			status = "okay";
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
		};

		enet1: ethernet@b1000 {
			status = "okay";
			phy-handle = <&phy2>;
			phy-connection-type = "rgmii-id";
		};

		enet2: ethernet@b2000 {
			status = "disabled";
		};

		usb@22000 {
			status = "disabled";
		};

		usb@23000 {
			status = "disabled";
		};
	};

	pci0: pcie@ffe09000 {
		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
		reg = <0 0xffe09000 0 0x1000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci1: pcie@ffe0a000 {
		reg = <0 0xffe0a000 0 0x1000>;
		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

};
/include/ "fsl/p1020si-post.dtsi"